Charge coupled devices (hereinafter also referred to as CCD's) have found wide acceptance as shift registers for transporting charge in semiconductive substrates. A series of laterally spaced gate electrodes adjacent but conductively separated from the semiconductive substrate are relied upon to transport the charge in discrete steps within the semiconductive substrate. Each charge transfer step is achieved by proper poential biasing of gate electrodes so that charge is attracted from one charge storage region to a next adjacent charge storage region in the semiconductive substrate.
Three phase CCD's, such as those described in Kahng U.S. Pat. No. 3,700,932, are among the simplest to construct. In FIG. 1 is shown a schematic diagram of a three phase CCD 100 comprised of a semiconductive substrate 101 of a first, N or P, conductivity type. An insulative layer 103 overlies the semiconductive substrate, and a series of spaced apart conductive gate electrodes overlie the insulative layer. The gate electrodes consist of a first set of gate electrodes 105 electrically connected to a .PHI..sub.1 power supply; a second set of gate electrodes 107 electrically connected to a .PHI..sub.2 power supply; and a third set of gate electrodes 109 electrically connected to a .PHI..sub.3 power supply.
The manner in which the three phase CCD laterally transports charge can be appreciated by reference to potential diagrams of FIGS. 2 through 4. In the initial condition shown in .PHI..sub.1 gate electrodes are electrically biased to attract minority charge carriers in the semiconductive substrate. For example, if the semiconductive substrate exhibits P type conductivity, the minority charge carriers are electrons, and the .PHI..sub.1 electrodes are positively biased to attract the electrons. Referring to FIG. 2, with the exemplary conditions above, the direction of positive potential is down, and the electrons 111 are held in potential wells 113, which are physically located beneath the electrodes 105. The gate elctrodes 107 and 109 are shown in FIG. 2 as being at the same potential, which is negative relative to the gate electrodes 105.
The electrons 111 in each potential well are laterally transported by first biasing the .PHI..sub.2 power power supply to the .PHI..sub.1 potential as shown in FIG. 3, thereby allowing the electrons 111 to spread beneath adjacent pairs of gate electrodes 105 and 107, and then biasing the .PHI..sub.1 power supply negatively so that the potential well is reformed beneath the gate electrodes 107, as shown in FIG. 4. Further lateral shifting is achieved by applying the above described procedure to successive pairings of gate electrodes.
For ease of illustration the simple laterally spaced gate electrode constructions are shown, but the potential variations resulting are ignored, since they can be minimized by known techniques for minimizing gate lateral spacing, such as those illustrated by Smith et al U.S. Pat. No. 3,921,195.
While three phase CCD's are simple in construction, the three phase clocking required for charge transport has been regarded as disadvantageous, and the art has sought to construct a CCD capable of being driven by a two phase clock. To be driven by a two phase clock, the CCD must be modified in construction to directionally bias charge transfer.
An early two phase CCD, such as described in Kahng et al U.S. Pat. No. 3,651,349, is shown in FIG. 5, wherein the CCD 200 is comprised of a semiconductive substrate 201 of a first, N or P, conductivity type. An insulative layer formed as a succession of alternate thinner portions 203 and thicker portions 205 overlies the semiconductive substrate, and a series of spaced apart conductive gate electrodes each overlying one thicker and one adjacent thinner portion of the insulative layer. The gate electrodes consist of a first set of gate electrodes 207 electrically connected to a .PHI..sub.1 power supply and a second set of gate electrodes 209 electrically connected to a .PHI..sub.2 power supply.
The operation of the two phase CCD 200 can be appreciated by reference to potential diagrams 6 and 7. Assuming the semiconductive substrate 201 is of P type conductivity and the .PHI..sub.1 power supply is initially biased positively, electrons 211 are initially confined to potential wells 213 which in this instance are physically located beneath the portions of the first gate electrodes 207 overlying the thinner portions 203 of the insulative layer. The second set of gate electrodes 209 is related in potential to the first set so that the potential of the portions of the gate electrodes 209 overlying the thinner portions of the insulative layer are at a potential equal to that of the portions of the first set of gate electrodes overlying the thicker portions of the insulative layer. This is shown in FIG. 6 as the uniform potential region 215.
When the relative potentials of the .PHI..sub.1 and .PHI..sub.2 power supplies are reversed, as shown in FIG. 7, the electrons 211 and potential well 213 are shifted to beneath the portions of the second set of gate electrodes 209 overlying the thinner portions 203 of the insulative layer. In shifting between their FIG. 6 and FIG. 7 positions the electrons 211 traverse the essentially uniform potential region 215 in FIG. 7.
Two phase CCD's such as CCD 200 have been found disadvantageous to manufacture, since the insulative layer must be formed in muliple steps to achieve the required thickness differences. Further, this nonuniformity of the insulative layer requires portions of the gate electrodes to lie in different planes, thereby also complicating their fabrication.
The art has therefore shown a preference for two phase CCD's having a simpler insulative layer and gate electrode construction relying on zones of increased impurity dopant concentration in the semiconductive substrate for directional biasing of charge transfer, as illustrated by Krambeck U.S. Pat. No. 3,789,267. Such CCD's are illustrated by CCD 300 in FIG. 8, in which a semiconductive substrate 301 of a first conductivity type supports an insulative layer 303 on which interlaid sets of gate electrodes 305 and 307 connected to the .PHI..sub.1 and .PHI..sub.2 power sources, respectively, are positioned. As shown, zones 309 are formed in the semiconductive substrate. The zones exhibit a higher level of impurity doping than the surrounding portions of the semiconductive substrate. The zones can also be of the first conductivity type, as taught by Krambeck U.S. Pat. No. 3,789,267, or can alteratively be of a second, opposite conductivity type, as taught by Tasch et al U.S. Pat. No. 4,035,906.
When the higher dopant level zones 309 are of the first conductivity type and exactly aligned with the left edges of the gate electrodes, as shown in FIG. 8, charge is transferred as described above by reference to the potential diagrams of FIGS. 6 and 7. When the higher dopant level zones are of the second conductivity type and exactly aligned with the right edges of the gate electrodes, charge is transferred as described above by reference to the potential diagrams of FIGS. 6 and 7. Stated another way, when the higher dopant level zones are of the second conductivity type and located as shown in FIGS. 8, charge is transferred as described above by reference to the potential diagrams of FIGS. 6 and 7, except that the direction of transfer is reversed.
The art has heretofore encountered some difficulty in consistently constructing to satisfy desired performance criteria two phase CCD's with implanted doping impurity zones to bias directionally charge transfer.
One of the major difficulties encountered is the necessity of accurately aligning the edges of the higher dopant level zones with the overlying edges of the gate electrodes. This is illusrated by the CCD 400 schematically diagrammed in FIG. 9. The CCD 400 is identical to the CCD 300, except that the othewise corresponding higher dopant level zones 409 are each displaced laterally so that the edge 411a lying nearest the next adjacent gate electrode is actually recessed beneath the edge 411b of the overlying gate electrode rather than being directly vertically aligned, as is the case in CCD 300.
The impact on performance of failing to align the higher dopant level zones and gate electrode edges can be appreciated by referring to the potential diagrams of FIGS. 10 and 11, which correspond to those of FIGS. 6 and 7, except for differences imparted by the above described misalignment of the gate electrode and zone edges. Assuming that charge to be transported is initially present in the potential wells 413 in FIG. 10, it is apparent that reversing the relative biasing of the two phase power supply cannot succeed in transporting the charge in tact to the potential wells 413 in FIG. 11. Instead a portion of the charge will be trapped in the unwanted potential wells 414, which result from the misalignment of the higher dopant level zone and gate electrode edges.
FIG. 12 is a schematic diagram of a CCD 500 identical to CCD 300, but differing in that the higher dopant level zones 509 present edges 511a that extend laterally beyond the edges 511b of the overlying gate electrodes. The disruption of charge transfer can be appreciated by reference to the potential diagrams of FIGS. 13 and 14, which correspond to those of FIGS. 6 and 7, except for differences imparted by the above described misalignment of the gate electrode and zone edges. Assuming that charge to be transported is initially present in the potential wells 513 in FIG. 13, it is apparent that reversing the relative biasing of the two phase power supply cannot succeed in transporting the charge to the potential wells 513 in FIG. 14. The reason is that the misalignment of the higher dopant level zone and gate electrode edges in the manner shown in FIG. 12 creates unwanted potential barriers 515 that disrupt charge transfer from a .PHI..sub.1 potential well to a .PHI..sub.2 potential well and vice versa.
Approaches heretofore disclosed in the art for manufacturing two phase CCD's with higher dopant level zones in the semiconductive substrate to directionally bias charge transport have suffered a number of limitations. The earliest manufacturing approaches relied upon accurate edge alignments of masks successively employed during fabrication to achive zone and gate electrode edge alignments. As gate electrode areas have decreased, these accurate mask alignments have become increasingly more essential to acceptable performance and more difficult to realize. A variety of manufacturing compromises have been resorted to, such as doubling the number of gate electrodes and externally wiring adjacent plate pairs to a common potential source; introducing higher dopant level zones for one phase at a different processing stage than those for the remaining phase, thereby risking nonuniformity of the higher dopant level zones; and working out self-aligning techniques for one set of gate electrodes and higher dopant level zones while requiring a different approach for the remaining set or sets of gate electrodes and higher dopant level zones.
In addition to three phase CCD's and two phase CCD's there are uniphase CCD's, commonly alternatively referred to as virtual phase CCD's. Typical virtual phase CCD's are described in Fry et al U.S. Pat. No. 4,047,215 and Hynecek U.S. Pat. No. 4,229,752. Virtual phase CCD's differ in construction from the two phase CCD's described above in that the .PHI..sub.2 gate electrodes are replaced by virtual phase electrodes formed by an additional uniform diffusion of impurity ions into the semiconductive substrate in areas which would otherwise underlie the .PHI..sub.2 gate electrodes. The virtual phase electrodes are used to uniformly fix or pin the potential profile of these substrate regions. To conduct charge the .PHI..sub.1 gate electrodes are driven by a single phase clock which cycles the potential profile of the regions of the semiconductive substrate underlying the .PHI..sub.1 gate electrodes above and below the fixed potential profile imposed by the virtual phase electrodes. Virtual phase CCD's require the same potential profiles as two phase CCD's, both in the .PHI..sub.1 gate electrode and virtual electrode regions, to successfully directionally bias charge transfer. Edge misalignments of the type described above with reference to FIG. 9 through 14 for two phase CCD's produce similar charge transfer barriers and wells in virtual phase CCD's.
A process for the preparation of two phase and virtual phase CCD's is disclosed by Anthony et al U.S. Pat. No. 3,927,468. Referring to FIG. 15, a P conductivity type monocrystalline silicon substrate 601 is provided with a silicon dioxide layer 603 grown on one major surface. A silicon nitride layer 605 overlies the oxide layer. A polycrystalline silicon (hereinafter also referred to as P-Si) layer 607 overlies the nitride layer, and a second silicon nitride layer 609 overlies the P-Si layer. A photoresist layer 611 overlies the second silicon nitride layer.
Referring to FIG. 16, to form charge transfer direction biasing implants in the silicon substrate Anthony et al first patterns the photoresist layer into segments 611a defining openings 613 therebetween. By etching through the openings the silicon nitride layer 609 is divided into barrier segments 609a, thereby extending the openings to the surface of the P-Si layer. By implanting through the P-Si layer, the silicon nitride layer 605, and the grown silicon dioxide layer 603, additional P conductivity type ions are implanted in the silicon substrate creating charge transfer direction biasing implants at spaced local zones 615.
Anthony et al then undertakes to form a set of .PHI..sub.1 gate electrodes overlying every other local zone. This is accomplished by removing the photoresist segments 611a and growing silicon dioxide in the openings between adjacent silicon nitride segments. The grown silicon silicon dioxide forms barrier segments 617a, as shown in FIG. 17. A patterned photoresist 619 is located to overlie and protect alternate of the first barrier segments 609a. The unprotected silicon nitride barrier segments are removed by etching, as indicated by dashed lines 609b.
Anthony et al next removes alternate of the silicon dioxide barrier segments. The photoresist 619 is removed. Referring to FIG. 18, a patterned photoresist 623 is located to overlie and protect alternate of the silicon dioxide barrier segments segments, allowing the unprotected silicon dioxide barrier segments to be removed by etching, as indicated at 617b. The photoresist 623 is then removed.
Each two contiguous silicon nitride and silicon dioxide barrier segments together form a barrier overlying the P-Si layer in spaced relation to adjacent barriers. By etching the P-Si layer using the barriers for protection a first set of gate electrodes can be formed.
The process of Anthony et al has some notable disadvantages. First, the selection of materials for forming the barrier segments is quite limited as each must be capable of being selectively etched under conditions to which the other is resistant to etching and both must be capable of resisting etching while the P-Si layer is being etched.
The use by Anthony et al of grown silicon dioxide to form barrier segments leads to further disadvantages. The silicon dioxide is grown by using the P-Si layer as a soruce of silicon. This locally thins the P-Si layer. Referring to FIG. 19, a stage of fabrication by the process of Anthony et al is shown at which the P-Si layer has been etched away in areas not protected by an overlying barrier. This produces gate electrodes each having a thicker portion 607a formed beneath a silicon nitride barrier segment and a thinner portion 607b formed beneath a silicon dioxide barrier segment. As shown in FIG. 19 the silicon nitride barrier segments have been removed by etching and an overall protective silicon dioxide layer 625 overlies all exposed areas of each gate electrode. Neither the gate electrodes nor the protective dioxide layers are of uniform thickness. These surface nonuniformities can lead to both optical disadvantages (e.g., light scattering) and device fabrication disadvantages resulting from nonplanar surfaces. Anthony et al further shows misalignment of the thinned edge of the gate electrodes and the edge of the underlying implant zone 615.
In addition to the limitations of the Anthony et al process which are acknowledged, there are additional disadvantages which result from using grown silicon dioxide and silicon nitride in combination to form barrier segments. FIG. 20 is an enlarged view of two silicon nitride barrier segments 609a defining an opening 613 on a P-Si layer 607. When silicon dioxide is grown at the P-Si layer surface, the silicon dioxide growth is not laterally confined to the opening 613. As shown in FIG. 21, the silicon dioxide barrier segment 617a covers the entire opening and additionally grows beneath the silicon nitride barrier segments adjacent the opening, forcing these adjacent barrier segment away from the P-silicon layer. This phenomenon is referred to by those skilled in the art as the "bird's beak" effect. Where a limited oxide etch is performed, as is commonly practiced to removed incidental silicon dioxide that has been formed on the surface of the silicon nitride, thereby improving the selective etching of silicon nitride, the upper configuration of the silicon dioxide barrier segment can take the configuration indicated by the dashed line 627. The vertical line 629 shows the lateral extent of the bird's beak, while the vertical line 631 shows the original lateral extent of the opening 613 and therefore the lateral extent of the implant zone. The spacing between the vertical lines, indicated by arrow 633, is a measure of zone and electrode edge misalignment. A typical bird's beak extension corresponding to the length of arrow 633 is 700 to 1000 Angstroms.
In addition to the bird's beak effect, the growth of silicon dioxide on the P-Si layer has other disadvantageous effects. Growth of silicon dioxide requires temperatures in excess of 600.degree. C. and more typically in the range of from 800.degree. to 950.degree. C. These temperatures are high enough that internal migration of lattice and intersticial ions in the monocrystalline silicon substrate can and do occur. In addition to allowing migration of implanted ions, also contributing to edge misalignments, other unwanted internal ion effects can result, such as interference with internal gettering and dopant ion clustering. Physical defects, such as substrate warping, can also occur on heating. Additionally, no organic material can survive the temperatures at which silicon dioxide is grown. Still further, the growth of silicon dioxide on silicon produces localized crystal lattice stresses that can produce unwanted effects. These stresses can extend down to the monocrystalline substrate producing unwanted lattice perturbations.